Mathematical Foundations of AI-Based Secure Physical Design Verification

Abstract

Concerns about hardware security are raised by the increasing dependence on third-party Semiconductor Intellectual Property in system-on-chip design, especially during physical design verification. Traditional rule-based verification methods, such as Design Rule Checking (DRC) and Layout vs. Schematic (LVS) checking, together with side-channel analysis indicated apparent deficiencies in dealing with new forms of threat. The impossibility of distinguishing dependable from malicious insertions in ICs makes it hard to prevent such dangers as hardware Trojans (HTs); side-channel vulnerabilities remain everywhere, and modifications at various stages of the manufacturing process can be hard to detect. This thesis addresses these security challenges by defining a theoretical AI-driven framework for secure physical design verification that couples graph neural network models (GNNs) and probabilistic modeling with constraints optimized to maximize IC security. This approach views physical design verification as graph-based machine learning: GNNs identify unauthorized modifications or discrepancies between the layout and circuit netlist through the acquisition of behavioral metrics and structural feature extraction of netlist data. A probabilistic DRC model is derived after processing some learning data using recurrent algorithms. This model departs from the rigid rules of traditional deterministic DRC in that it uses machine learning-based predictions to estimate the likelihood that design rules will be violated. Also, we can model mathematical foundations for the secure routing as a constrained pathfinding problem for all myths addressed above concerning these different methods—moves are optimized to avoid sources of security problems. These problems might include crosstalk-induced leakage and electromagnetic sidechannel threats. Lagrange multipliers and Karush-Kuhn-Tucker (KKT) conditions are included in verification to maintain security constraints while ensuring efficient use of resources. Then, HT detection is reformulated as GNN-based node embeddings, whose information propagation throughout the circuit graph picks up modifications at boundary nodes and those less deep in the structure. As an alternative to experience-based anomaly detection proposed in earlier work, a theoretical softmaxbased anomaly classification framework is put forward here to model HT insertion probabilities, gathering acceptable anomalies at various levels of circuit design from RTL-level to Gate-level as necessary. The capturing of side-channel signals becomes the focus of a deep learning-based theoretical run-time anomaly detection model, aiming at power and electromagnetic (EM) leakage patterns so that all potential threats can be detected early on. This theoretical framework provides a conceptual methodology for scalable, automated, and robust security verification in modern ICs through graph-based learning, and constrained optimization methods. It lays a foundation to advance secure semiconductor designs further using AI-driven techniques without recourse to benchmarks or empirical validations.